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Microchip Technology /ATSAMD51P20A /OSCCTRL /DPLL[0] /DPLLSTATUS

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Interpret as DPLLSTATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCK)LOCK 0 (CLKRDY)CLKRDY

Description

DPLL Status

Fields

LOCK

DPLL Lock Status
CLKRDY

DPLL Clock Ready

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data